ad is multiplex address data line bus
the 8085 microprocessor is a 8-bit microprocessor and these are bidirectional but the address lines are unidirectional.these address lines are used to address the location of the instruction in memory .these data lines are used to transfer data between processor and peripheral devices. when the address of the instruction will be recognized by the address lines the data will be send to the processor therefore the 16 address lines are not act as a data lines in 8085
Microprocessor has 16 address lines and microcontroller has 20 address lines
Data Lines: Carry the actual data transmitted between components. Address Lines: Specify the memory address for data storage or retrieval. Control Lines: Manage the flow of data within the system by indicating when data is being transferred or when a specific operation is required. Clock Lines: Synchronize the timing of operations within the system to ensure data is transmitted and received at the correct times.
A 2K X 8 memory requires 11 address lines and 8 data lines
17 address lines and 8 data lines. 2^17=128k
12
1)address lines to refer to the address of a block 2)data lines for data transfer 3)IC chips 4 processing data
Memory Read refers to the process when 1) HL pair holds the address which is to be read 2) this address is placed on address lines (ALE : Address Latch Enable, must be high at this moment) 3) then Memory Read Control Signal (MEMR) goes high to signify that at this moment we need to read (get) data from memory. 4) Then ALE goes low and data is placed on lower bit address lines ( Because data lines are multiplexed with lower byte address line) 5) After getting the data in the register, ALE again goes High, MEMR goes low.
ALE is a signal that means that the data bus contains the lower order address bus values. External hardware should strobe the data bus during ALE time, and lock it on the falling edge of ALE.
System pins: Include the clock and reset pins. Address and data pins: Include 32 lines that are time multiplexed for addresses and data. Interface control pins: Control the timing of transactions and provide coordination among initiators and targets. Arbitration pins: Unlike the other PCI signal lines, these are not shared lines. Rather, each PCI master has its own pair of arbitration lines that connect it directly to the PCI bus arbiter. Error Reporting pins: Used to report parity and other errors. Interrupt Pins: These are provided for PCI devices that must generate requests for service. Cache support pins: These pins are needed to support a memory on PCI that can be cached in the processor or another device. 64-bit Bus extension pins: Include 32 lines that are time multiplexed for addresses and data and that are combined with the mandatory address/data lines to form a 64-bit address/data bus. JTAG/Boundary Scan Pins: These signal lines support testing procedures defined in IEEE Standard 1149.1.
1)address lines to refer to the address of a block 2)data lines for data transfer 3)IC chips 4 processing data