How program and data memory fetches can be overlapped in a Harvard architecture?
In Harvard architecture, the program memory space is distinct
from data memory space. Such architecture requiring two
connections. It can perform instruction fetch ( from program memory
) and data memory fetch simultaneously , by adopting a pipelined
instruction execution approach, as shown below.
A typical instruction execution consists of performing Fetch
instruction, Decode instruction, Fetch operands, execution
operation , store results. Then, by adopting a pipelined approach,
which is possible in Harvard architecture, it is evident that the
instruction throughput increases by overlapping. It is simple to
imagine that in the above case, if all the above states are
executed "one after the other" , the execution time of the
instruction will be longer than when it is pipelined.