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What is STD logic in vhdl?

Anonymous

∙ 12y ago

Updated: 9/18/2023

In VHDL, std_logic is a data type. It is assigned to input and / or output variables. It means that the variable is a standard logic type i. e. a logic bit which accepts or provides one bit data, either 1 or 0.

Wiki User

∙ 12y ago

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