The low state dc noise margin for TTL dates is 0.3v and the high state noise margin is 0.7v
because TTL have a bias input setup to eliminate noise therefore the output will follow the logic one input if left open
Unused ttl inputs would normally default to logic 1 if left floating. but these inputs could act as antennas under certain conditions and they could pick up noise which can cause the circuit to malfunction. it is better to tie unused inputs to Vcc through a 1k resistor (74LS, 74XX etc) or simply return the inputs to ground. for most other ttl families, the 1k resistor might not be required.- Stan (Nigeria)
whis is Endurance mors or ttl
TTL
Unused ttl inputs would normally default to logic 1 if left floating. but these inputs could act as antennas under certain conditions and they could pick up noise which can cause the circuit to malfunction.
TTL stands for Time To Live
TTL is set to 40
TTL is faster and does not lose amplitude
The full form of TTL is Time To Live
Here are the propagation delays for these gatesa) ECL = 2nsb) TTL = 1.5-33ns depending on the type of TTL. Conventional TTL is 9ns, Advanced Schottky TTL is 1.5nsc) RTL = 25nsd) CMOS = 5-20ns depending on if it is conventional CMOS, TTL pin compatible CMOS, high speed TPC CMOS or TTL compatible CMOSSo the fastest would be the Advanced Schottky TTL (74ASxx) at 1.5ns but the choice simply said TTL which I would interpret as Conventional TTL (74xx/54xx) which would have a propagation delay at 9ns.So the winner is ... (a) ECL which has a propagation delay at 2ns.
The main advantage of ECL over TTL is speed.