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DQS = data strobe. When data is read from DRAM using the DQ pins, DQS is asserted so that memory controller can use that to read data. When memory controller writes to DRAM, it asserts DQS when DQ pins have the data to be written.

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17y ago
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12y ago

Data queue strobe

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Q: What is DQS in DDR3 SDRAM?
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Related questions

Why does the DDR3 has two pair DQS in per data lane?

The DDR3 has two pairs of DQS in per data lane for optimal termination values. IT is also for signal topology and the possible swapping of the DDR3's memory side pin.Ê


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It is not very noticeable if you upgrade your memory on your computer.


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The fastest technology in actual is laan, laan is the longest and most profound memory ever.


Where can one purchase a DDR3 Sdram?

You can purchase a DDR3 SDRAM for your computer from places such as Fry's Electronics, Best Buy, Newegg, Tiger Direct, Amazon and eBay. Before buying, make sure it will be compatible with your computer.


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When was DQS created?

DQS was created in 1985.


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This laptop comes with DDR3 SDRAM, and GMA 500MHD, graphic capabilities.


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The Z0FU-250GB comes with a standard of 2GB DDR3 SDRAM but is upgradable to a maximum of 4GB.


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