If you look at the 7486 IC datasheet you can see, it have 4 independence XOR gates with 2 inputs. So you can only use 2 inputs if you see it like that. But if you understand the truth table of XOR gate you can have 3 input application using 7486 IC. Here I will show you how. 1.Get the first 2 input into the first XOR gate. 2.Then get the 3rd input together with the Output from the first 2 input XOR gate into another gate. 3.This output should be the result of 3 input XOR gate. Check this output with 3 input truth table to confirm the answer.
For 2-input EX-OR gate, if one input is A, the other input is B, and the output is Y. Then the Boolean expression for EX-OR (XOR) function (gate) is Y=A⊕B The output Y is true if either input A or if input B is true, but not both.Y= ( (A and NOT B) or (NOT A and B) ) ;
Three 2-input XOR gates and one 3-input NOR gate will do the work. Connect each output of each XOR gate to one input of the 3-input NOR gate and apply the two 3-bit words to the inputs of the XOR gates. If X (X2X1X0) and Y(Y2Y1Y0) are two 3-bit words, X2 and Y2 will connect to one XOR gate, X1 and Y1 to the next XOR gate and X0 and Y0 to the last XOR gate. You could see the result of the operation on a LED connected to the output of the NOR gate. Other implementations are also possible of course. The solution above is absolutely correct, but includes a 3 input gate. If the task is to use only two input gates, then a small change will be needed. Take the outputs from any two XOR gates into a 2 input OR gate. Then take the output of the OR gate and the output of the third XOR gate into a 2 input NOR gate. The operation remains identical to the first solution but adheres to the brief of using gates with 2 inputs. In the real world, there is probably no reason to impose such a limitation on a design so the first solution would normally be the preferred route to take.
To produce a 3-input OR gate when only 2-input OR gates are available: Use 3 OR gates Inputs to Gate A are input 1 and input 2 Input to Gate B is input 3 (if 2 inputs are necessary, include input 3 and FALSE) Inputs to Gate C are outputs from Gate 1 and Gate 2 === If input 1 OR 2 is TRUE, output of Gate A will be TRUE. If input 3 is TRUE, output of Gate B will be TRUE. If output of Gate A OR Gate B is TRUE, output from Gate C will be TRUE. That is if one ore more of Inputs 1, 2 or 3 is TRUE, the result will be TRUE. Otherwise, output of Gate C will be FALSE.
Its possible to design a 4-i/p xor gate using only 2-i/p nand gates Although the design turns out to be quite complex and comprises of 21 NAND gates : F = (A'B+AB')(C'D'+CD) + (A'B'+AB)(C'D+CD') Above given equation is the o/p equation for the circuit .
To produce a 3-input OR gate when only 2-input OR gates are available: Use 3 OR gates Inputs to Gate A are input 1 and input 2 Input to Gate B is input 3 (if 2 inputs are necessary, include input...
this shows you everything you need about them Pin Number Description 1 A Input Gate 1 2 B Input Gate 1 3 Y Output Gate 1 4 A Input Gate 2 5 B Input Gate 2 6 Y Output Gate 2 7 Ground 8 Y Output Gate 3 9 B Input Gate 3 10 A Input Gate 3 11 Y Output Gate 4 12 B Input Gate 4 13 A Input Gate 4 14 Positive Supply
output is feedback in input
You would connect the output of the first AND gate to one input of the second AND gate. You are left with 2 inputs on the first AND gate and 1 input on the second AND gate. The final output is from the second AND gate.
Use 4 NOR gates. For the 1st NOR gate, inputs should be x' and y For the 2nd NOR gate,inputs should be y' and x The outputs of NOR 1 and NOR 2 are taken as inputs of NOR gate 3 The output of NOR 3 is the complemented form of the output required, so, just complement the output of NOR gate 3 with another NOR gate and Viola!, you have your HALF ADDER OUTPUT PS:I have used a double rail logic, where both x:x' and y:y' are available
asdfghjkl;' s-sum and c'-carry see for half adder s=a(xor)b and c'=ab for full adder s=a(xor)b(xor)c and c=ab+bc+ac or ab+c(a(xor)b) we can convert two half adder to full adder with help of and or gate. . . ! we got two half adder * for first half adder input is a and b therefore. . .s=a(xor)b and c'=ab * for second half adder input is a(xor)b and c therefore. . .s=a(xor)b(xor)c and c' is (a(xor)b)c note: now connect the c' of first half adder and second half adder to 'or' gate resulting is ab+c(a(xor)b)
you will need 2 two input AND gates to do this. connect the output of the first to one input of the second. you now have a three input AND gate. just remember when calculating timing that 2 inputs of the 3 have twice the gate delay of the remaining input, thus the output will have skew and possibly glitches. if timing is critical or glitching can't be tolerated it may be best to use an actual three input AND instead of kludging one.