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Question_1: The following code reads port 0x21 (interrupt mask register) of PIC (Programmable Interrupt Controller), sets the 2nd bit that is mapped to IRQ1 and writes it back to port 0x21. As a result keyboard interrupt will be disabled as IRQ1 is used by keyboard. [10 marks] ; disable keyboard interrupt in PIC mask register 01 [org 0x0100] 02 in al, 0x21 ; read interrupt mask register 03 or al, 2 ; set bit for IRQ1 04 out 0x21, al ; write back mask register 05 mov ax, 0x4c00 ; terminate program 06 int 0x21 Modify instruction_03 for the following: I. set bit for IRQ0 II. set bit for IRQ6 III. set bits for IRQ1, IRQ3 and IRQ4 IV. clear bit for IRQ5 V. clear bits for IRQ2, IRQ5, IRQ6 and IRQ7

Question_2: Suggest a reason for the following: [5 marks] I. We should disable interrupts while hooking interrupt 8h, i.e. while placing its segment and offset in the interrupt vector table. II. We need not do this for interrupt 80h.

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Q: Why you should disable interrupts while hooking interrupt 8H?
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Should any device be allowed to interrupt CPU while another interrupts are being serviced?

It is possible to allow nested interrupts. This is often done when there is a heirarchy of interrupts, some with higher priority than others. In order for this to work, the second interrupt must not be allowed to influence the progress of the first interrupt. We call this being "thread safe". In a nested scheme, an interrupt mask is set so that higher priority interrupts can be permitted, while blocking interrupts of the same or lower priority, and then interrupts are reenabled during the interrupt service routine. At the conclusion of the first routine, interrupts are disabled again, the mask is restored, and the normal interrupt return sequence is executed. In the 8085, this can be supported using the Read Interrupt Mask (RIM) and Set Interrupt Mask (SIM) instructions. While not strictly required, the logical priority is often INTR, RST5.5, RST6.6, RST7.5, and then TRAP, in order of increasing priority.


Which are the highest priority interrupts?

when interrupts requests arrive from two or more devices simultaneously , the process has to decide which request should be serviced first and which one should delayed. the processor takes the decision with the help of interrupt priorities.


Different between maskable and non-maskable interrupt?

Maskable interrupts trigger events are not always important and so the programmer can decide that the event should not cause a program to jump. Nonmaskable interrupts can not be ignored by the programmer and therefore they have absolute priority.


What is an interrupt and how are multiple interrupts dealt with?

An Interrupt is a signal that goes into a microprocessor that tells it something has happened that needs attention. There are generally dedicated pins on the microprocessor, often called "Int" (for Interrupt) and "NMI" (for Non-Maskable Interrupt). For a microprocessor, an interrupt signal is like the bell on a telephone is for you; it's a notice that you should stop what you are doing now and deal with this issue that has come up. Exact procedures for dealing with an interrupt vary from one microprocessor to another; generally, the microprocessor puts out a signal that says "Where should I go, then?" and a piece of hardware, the Interrupt Controller, then responds with a signal that tells it which condition has happened. The processor then starts processing the indicated piece of code, and that piece of code handles the condition. The Interrupt Controller often handles setting priority for interrupts, accepting a number of signals (often four), and setting priorities on each. It will trigger another interrupt in the middle of processing one if the new interrupt is a higher priority than the one that is already being processed, or will hold on to the lower priority one until the CPU is finished with a higher-priority one. The CPU can often "disable interrupts" when it is doing something time-critical. At such times, the only interrupt that can occur is the Non-Maskable Interrupt, which is generally reserved for critical error conditions that have to be dealt with immediately no matter what else is going on.


What is non maskable interrupt interrupt?

Non Maskable interrupts (such as those generated by power failure) cannot be blocked by the CPU. Maskable interrupts are common device interrupts such as disk/network adapters interrupts which can be blocked by the CPU.


Interrupt driven IO?

Whenever a data transfer to or from the managed hardware might be delayed for any reason, the driver writer should implement buffering. Data buffers help to detach data transmission and reception from the write and read system calls, and overall system performance benefits.A good buffering mechanism leads to interrupt-driven I/O, in which an input buffer is filled at interrupt time and is emptied by processes that read the device; an output buffer is filled by processes that write to the device and is emptied at interrupt time. An example of interrupt-driven output is the implementation of /dev/shortprint.For interrupt-driven data transfer to happen successfully, the hardware should be able to generate interrupts with the following semantics:For input, the device interrupts the processor when new data has arrived and is ready to be retrieved by the system processor. The actual actions to perform depend on whether the device uses I/O ports, memory mapping, or DMA.For output, the device delivers an interrupt either when it is ready to accept new data or to acknowledge a successful data transfer. Memory-mapped and DMA-capable devices usually generate interrupts to tell the system they are done with the buffer.


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"You should not interrupt class," the teacher scolded the boy.


Should you interrupt in class?

No.


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